1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same, more specifically relates to a semiconductor device having a bipolar transistor and methods for producing the same.
2. Description of the Related Art
Transistors used in semiconductor devices can be roughly divided into metal-oxide-semiconductor field effect transistors (MOSFET) and bipolar transistors. MOSFET's include n-channel MOSFET's, p-channel MOSFET's, and complementary MOSFET's (CMOSFET's) using the two. On the other hand, bipolar transistors include npn junction type transistors and pnp junction type transistors. A bipolar transistor is capable of operating at a high speed compared with a MOSFET because the bipolar transistor itself operates at a high speed. Further, the transfer conductance of a bipolar transistor is large, and the ability to drive a capacitive load is large.
Among the above bipolar transistors, a longitudinal pnp junction type bipolar transistor having a high withstand voltage is cross-sectionally shown in FIG. 1A as an example of the related art. An n-type epitaxial layer 20 is formed on a p-type semiconductor substrate 1 and covered with an insulating film 40. In a region where elements are electrically insulated (isolated) by a p.sup.+ -type buried layer 11 and p.sup.+ -type isolating layer 23, an n.sup.- -type pocket 2 is formed from near an interface between the p-type semiconductor substrate 1 and n-type epitaxial layer 20 to the p-type semiconductor substrate 1. A p.sup.+ -type buried layer 10 is formed on the n.sup.- -type pocket 2 and is connected to a p-type well 21 which reaches from the surface of the n-type epitaxial layer 20 to the p.sup.+ -type buried layer 10. An N.sup.+ -type graft base 24 and n-type base 25 are formed in the p-type well 21 and are connected to a base take-out electrode B from the opening portion of the insulating film 40. Also, a p.sup.+ -type emitter 26 is formed in the n-type base 25 and is connected to an emitter take-out electrode E. On the other hand, a p.sup.+ -type plug 22 is formed in the p-type well 21 so as to be connected to the p.sup.+ -type buried layer 10, and a p.sup.+ -type collector 27 is formed in the p.sup.+ -type plug 22 and is connected to a collector take-out electrode C.
In the above longitudinal pnp junction type bipolar transistor having a high withstand voltage, in a practical usage, a power source voltage is supplied to the n.sup.- -type pocket 2, a ground voltage is supplied to the p-type semiconductor substrate 1, and a voltage from the ground to a power source voltage is supplied to the p.sup.+ -type buried layer 10 which becomes the collector region. For use under a high power source voltage, it is necessary to set the breakdown withstand voltage high at junctions between the n.sup.- -type pocket 2 and p.sup.+ -type buried layer 10, the p-type semiconductor substrate 1 and p.sup.+ -type buried layer 10, and the n.sup.- -type pocket 2 and p-type semiconductor substrate 1.
Here, the relative concentrations of conductive impurities of each layer are shown in FIG. 1B. The p.sup.+ -type buried layer 10 which becomes the collector region is a region where most of the collector current flows and is normally formed to include high concentrations of p-type conductive impurities in order to lower the collector resistance. Also, at a pn junction, the lower the concentrations of conductive impurities of either of the p-side or n-side, the higher the breakdown withstand voltage, therefore the n.sup.- -type pocket 2 is formed to include n-type conductive impurities at low concentrations.
Furthermore, the withstand voltage between the p-type semiconductor substrate 1 and p.sup.+ -type buried layer 10 changes according to the total amount of conductive impurities included in the n.sup.- -type pocket 2 formed between them. The smaller the total amount of the conductive impurities, the easier a punch through occurs and the withstand voltage declines. Accordingly, for the n.sup.- -type pocket 2, it is necessary to raise the total amount of the conductive impurities while including conductive impurities at low concentrations. Therefore, it is necessary to form the n.sup.- -type pocket 2 to have a deep depth. For example, to obtain a withstand voltage of the 100V level, it is necessary to make the peak concentration of the n.sup.- -type pocket 2 about 1.times.10.sup.16 /cm.sup.-3 and the depth more than 7 to 9 .mu.m.
A method for producing the above longitudinal pnp junction type bipolar transistor having a high withstand voltage will be explained. First, as shown in FIG. 2A, an n.sup.- -type pocket 2 is formed by ion implantation of n-type conductive impurities into the p-type semiconductor substrate 1.
Next, as shown in FIG. 2B, conductive impurities are diffused in the n.sup.- -type pocket 2 to reach at least a depth of 14 to 16 .mu.m from the surface of the p-type semiconductor substrate 1 by a heating process at high temperature for a long time, for example, at 1200.degree. C. for 100 hours. As a result, the depth of the n.sup.- -type pocket 2 can be made more than 7 to 9 .mu.m at the time when a p.sup.+ -type buried layer is formed in a later procedure.
Next, as shown in FIG. 2C, a p.sup.+ -type buried layer 10 is formed in the n.sup.- -type pocket 2 and a p.sup.+ -type buried layer 11 for element isolation is formed in an element isolating region by ion implantation of p-type conductive impurities and diffusion by a heating process.
Next, as shown in FIG. 2D, an n-type epitaxial layer 20 is formed by epitaxial growth at the upper layer of the p-type semiconductor substrate 1.
Next, as shown in FIG. 2E, a p-type well 21 is formed which reaches to the p.sup.+ -type buried layer 10 from the surface of the n-type epitaxial layer 20. Further, a p.sup.+ -type plug 22 which reaches to the p.sup.+ -type buried layer 10 in the p-type well 21 and a p.sup.+ -type isolating layer 23 reaching to the p.sup.+ -type buried layer 11 in the element isolating region are formed respectively by ion implantation of p-type conductive impurities and diffusion by a heating process.
The succeeding steps include, for example, forming an n.sup.+ -type graft base 24 and n-type base 25 in the p-type well 21, forming a p.sup.+ -type emitter 26 in the n-type base 25, forming a p.sup.+ -type collector 27 in the p.sup.+ -plug 22, forming a base take-out electrode B, emitter take-out electrode E, and collector take-out electrode C respectively connected to them, and thereby forming a longitudinal pnp junction type bipolar transistor having a high withstand voltage shown in FIG. 1A.
In the above method of production of a longitudinal pnp junction type bipolar transistor having a high withstand voltage of the related art, however, a high temperature, long heating process of, for example, 1200.degree. C. and 100 hours, is required to form the n.sup.- -type pocket 2 including conductive impurities at low concentrations and having a deep depth. As a result, the productivity is remarkably low due to the long period for completion and low processing performance of a diffusion reactor.
To shorten the above long processing time for the heating process, the method of raising the temperature of the heating process can be considered, however, an ordinary quartz reactor core tube easily deforms due to a high temperature process so has to be exchanged frequently and the productivity declines. Also, a method of using carbonized silicon (SiC) as a reactor core tube which is hard to deform can be considered, however, in reality there is a disadvantage that it is difficult to prepare a tube with a large diameter.